The present application relates generally to semiconductor devices, and more specifically to dual strained channel devices and their methods of manufacture.
The integration of p-type metal oxide semiconductor (PMOS) logic with n-type metal oxide semiconductor (NMOS) logic on a single substrate poses a number of processing challenges, including the enhancement of disparate channel regions (e.g., a p-type channel that comprises compressively strained SiGe and an n-type channel that comprises tensile Si) as well as the accommodation of typical trench isolation modules, which introduce a thermal budget that can adversely affect performance of the channel materials.
A number of methods have been used to form integrated CMOS devices, including strain relaxed buffers to form semiconductor layers such as SiGe. May of these methods present several disadvantages, however, including long deposition times, rough surfaces, non-uniform stress, high residual strain, and high defect densities including high threading dislocation densities.
Accordingly, it would be advantageous to provide semiconductor device manufacturing methods that enable the integration of PMOS and NMOS structures while overcoming the challenges faced by the industry.